必过源码 - FPGA综合 http://159.75.147.240/forum.php?mod=forumdisplay&fid=70 Latest 20 threads of FPGA综合 Copyright(C) 必过源码 Discuz! Board by Comsenz Inc. Tue, 21 Apr 2026 22:46:24 +0000 60 http://159.75.147.240/static/image/common/logo_88_31.gif 必过源码 http://159.75.147.240/ Verilog编写的11阶FIR数字滤波器 http://159.75.147.240/forum.php?mod=viewthread&tid=16285 FPGA综合 admin Fri, 04 Apr 2025 06:32:26 +0000 基于FPGA的17阶FIR滤波器VHDL代码。文件附带了FIR数字滤波器理论的介绍 http://159.75.147.240/forum.php?mod=viewthread&tid=16284 FPGA综合 admin Fri, 04 Apr 2025 06:31:10 +0000 基于FPGA的1000阶FIR数字滤波器 http://159.75.147.240/forum.php?mod=viewthread&tid=16283 FPGA综合 admin Fri, 04 Apr 2025 06:29:06 +0000 基于FPGA的IIR数字滤波器的设计方案：AD转换模块、IIR滤波模块、DA转换模块 http://159.75.147.240/forum.php?mod=viewthread&tid=16282 FPGA综合 admin Fri, 04 Apr 2025 06:26:56 +0000 基于FPGA的并行FIR数字滤波器的实现 http://159.75.147.240/forum.php?mod=viewthread&tid=16281 FPGA综合 admin Fri, 04 Apr 2025 06:25:38 +0000 基于VHDL语言编写的FIR数字滤波器 http://159.75.147.240/forum.php?mod=viewthread&tid=16280 FPGA综合 admin Fri, 04 Apr 2025 06:23:03 +0000 可变分数延时FIR数字滤波器的FPGA设计与实现 http://159.75.147.240/forum.php?mod=viewthread&tid=16278 FPGA综合 admin Fri, 04 Apr 2025 06:19:11 +0000 FIR数字滤波器程序，采用VHDL编写，可用于FPGA电路 http://159.75.147.240/forum.php?mod=viewthread&tid=16277 FPGA综合 admin Wed, 02 Apr 2025 22:55:41 +0000 FPGA嵌入式应用之数字滤波器：里面有部分Matlab+VHDL http://159.75.147.240/forum.php?mod=viewthread&tid=16276 FPGA综合 admin Wed, 02 Apr 2025 22:54:40 +0000 数字滤波器Verilog源码 http://159.75.147.240/forum.php?mod=viewthread&tid=16275 FPGA综合 admin Wed, 02 Apr 2025 22:53:14 +0000 八阶巴特沃兹IIR数字滤波器，四个二阶节，Verilog代码实现，多路分时复用 http://159.75.147.240/forum.php?mod=viewthread&tid=16274 FPGA综合 admin Wed, 02 Apr 2025 22:52:04 +0000 Verilog的FIR数字滤波器：测试性能不错 http://159.75.147.240/forum.php?mod=viewthread&tid=16273 FPGA综合 admin Tue, 01 Apr 2025 17:27:13 +0000 FPGA实现数字滤波器，用VHDL语言实现的直接1型FIR滤波器 http://159.75.147.240/forum.php?mod=viewthread&tid=16270 FPGA综合 admin Tue, 01 Apr 2025 17:18:47 +0000 AES的Verilog实现,用于加密的算法硬件实现 http://159.75.147.240/forum.php?mod=viewthread&tid=16157 FPGA综合 admin Thu, 06 Feb 2025 05:23:05 +0000 AES算法的Verilog HDL实现 http://159.75.147.240/forum.php?mod=viewthread&tid=16155 FPGA综合 admin Thu, 06 Feb 2025 05:20:15 +0000 AES算法的Verilog代码，即AES算法IP核 http://159.75.147.240/forum.php?mod=viewthread&tid=16154 FPGA综合 admin Thu, 06 Feb 2025 05:18:52 +0000 AES算法的Verilog实现 http://159.75.147.240/forum.php?mod=viewthread&tid=16153 FPGA综合 admin Thu, 06 Feb 2025 05:17:42 +0000 基于FPGA的LVDS接口调试，简单易懂 http://159.75.147.240/forum.php?mod=viewthread&tid=15800 FPGA综合 admin Wed, 25 Dec 2024 18:11:23 +0000 利用硬件语言Verilog实现直方图均衡化 http://159.75.147.240/forum.php?mod=viewthread&tid=15799 FPGA综合 admin Wed, 25 Dec 2024 18:09:19 +0000 基于FPGA的三速以太网UDP协议栈设计 http://159.75.147.240/forum.php?mod=viewthread&tid=15796 FPGA综合 admin Wed, 25 Dec 2024 18:00:54 +0000